The present invention relates to methods of packaging semiconductor chips and packaged semiconductor chips, and more particularly to packaging methods and chips in which the package lid-to-chip alignment tolerances are not dictated by the alignment of the lid-carried gate contacts with the chip gate electrodes.
Packages for semiconductor chips protect time chip from the environment in which the chip is to be used and provide access to time electrical contacts that are found on the chip. Packages are available in a wide variety of configurations, some of which are hermetic (gas-tight), and the design thereof must consider the need to dissipate heat generated by the chip, the current and voltage carrying capacity of time chip and the surface topography of the chip. A goal is to provide ever smaller and lighter chip packages that can be manufactured without undue cost or complexity. Although it is known to change chip topography to accommodate packaging, the methods of doing so typically add layers on top of existing chip topography and thus increase the complexity of the chip and the chip manufacturing process. The present invention is a departure from known practices in that the chip is designed to accommodate packaging needs in a manner that benefits chip performance without increasing chip manufacturing complexity.
Semiconductor chips for which the present invention may find application include solid state power devices having a cellular topography, such as, but not limited to, MOSFETs, MOS gated semiconductor devices, including MOS controlled thyristors (MCTs), insulated gate bipolar transistors (IGBTs), conductivity modulated field effect transistors (COMFETs) and the like. By way of example, a chip 10 having a cellular topography may be seen in FIG. 1. Such chips are manufactured using known processes, such as the vertical double-diffused process called DMOS. Each chip may include tens of thousands of uniformly spaced cells 12 spaced 10 to 50 microns center to center (e.g., a 240 mil.sup.2 chip may have more than 250,000 cells.) Typically, two electrodes are located on the upper surface of the chip: a polysilicon gate electrode 14 in the spaces 16 between the cells 12 and a metal power electrode 18 that overlies all of the cells, including the intercellular spaces 16 covered by the gate electrode 14. The two electrodes are separated by an insulative layer 20. The source electrode 18 is on a top layer of the chip 10 and is exposed so that electrical contact may be made therewith. However, the gate electrode 14 underlies the source electrode 18 making contact therewith more difficult.
As shown in FIG. 1, one known method of electrically contacting the gate electrode 14 is to provide an additional metal layer to form a metal gate electrode bonding area 22 where electrical contact may be made, with the size of the gate bonding area generally determined by the nature of the bonding method used to connect a source of gate voltage thereto. However, this method increases manufacturing complexity of the chip and reduces the area of the chip which can be dedicated to cells (the active area) by the area of the metal gate bonding area 22 and its associated metal gate runners 24 that carry a gate signal throughout the chip. Because of their composition and cross-section, metal gate runners 24 carry a gate signal from the gate bonding area 22 to areas of the gate electrode 14 remote therefrom with fewer impedance losses than would be found if only the polysilicon gate electrode 14 itself were used to carry the gate signal.
The rate at which gate electrode voltage is carried over the surface of the chip is affected by a number of factors, including the speed of the driver circuit delivering the gate signal, parasitic package inductance, inherent gate capacitance, and the effective series resistance (ESR) of the polysilicon gate electrode. The ESR is also related to a number of factors, including the geometry of the polysilicon gate electrode and the resistance of the polysilicon. Interdigitated (i.e., between cell) metal gate runners have been used to reduce ESR. The metal gate runners are connected to the gate bonding area and may be carried on top of the source electrode (separated therefrom by a dielectric material) without reducing chip active area.
Examples of packaging for a cellular semiconductor chip may be seen in FIGS. 2 and 3 where the package 26 and chip 10 are in vertical cross-section with reference to FIG. 2 (described in related application Ser. No. 823,343), the package may include a tub 28 for holding the chip 10 and a lid 30 for protecting the upper surface 32 of the chip (and for sealing the chip 10 inside the package 26 when the package is hermetic). The tub 28 may comprise several pieces as shown in FIG. 2 or be formed from a single piece of appropriate material. As shown in FIG. 3 (described in related application Ser. No. 826,003), the upper surface of the chip 10 may be protected and/or sealed by placing a lid 30 over the upper surface and attaching the edge of the lid 30 to the edge of the chip 10 to obviate the need for the tub.
Electrical contacts 34 for conducting current to and from the chip 10 extend through the lid 30. As the electrical contacts 34 may be small in cross-sectional area, the area of contact with the chip electrodes 18 and 22 may be enlarged by the use of electrically conductive foils 36 and 38 in contact with the respective chip electrodes 18 and 22.
One of the problems encountered in the packaging process is the alignment of the lid 30 with the chip 10 so that the foils 36 and 38 only contact their associated chip electrodes 18 and For example, prior art package manufacturing processes have alignment tolerances of up to several hundred microns, typically 50 to 150 microns. To accommodate the lid alignment tolerances in the prior art, chip topography was changed to provide additional spacing between electrodes. However, this additional space reduced the amount of active area making the chip less efficient and more costly. This problem is illustrated in FIGS. 4 and 5 where FIG. 4 illustrates the bottom surface of the lid 30 of FIG. 3 and where FIG. 5 shows the top surface of the chip 10 of FIG. 3. As may be seen therein, the foils 36 and 38 on the lid bottom surface are aligned with the electrodes 18 and 22 on the upper surface of the chip 10 to provide the necessary electrical contact when the lid is positioned on top of the chip. The lid 30 may be bonded to tub 28 (FIG. 2) or chip 1 (FIG. 3) at the edges 40 thereof using known techniques.
Various techniques for bonding the foils 36 and 38 to the chip electrodes 18 and 22, and for bonding foils 36 and 38 to the lid 30, are known in the prior art and may be used in the present invention, including both solder bonds and direct solderless bonds such am compression bonding, ultrasonic bonding, thermosonic bonding, diffusion bonding, cold welding, resistance welding, laser welding and direct bonded copper.
The lid 30 may be a ceramic such as alumina, beryllium oxide or aluminum nitride. The foils 36 and 38 on the lid lower surface may be copper foils about 0.001 to 0.005 inches thick that may be direct bonded copper to the lid 30. Thicker foils may be used for higher conductivity, although thicker foils may increase stress on the chip and the package. Thinner foils reduce conductivity and may increase the risk of tearing or leaking. The foils 36 and 38 may be bonded to the electrodes 18 and 22 on the upper surface of the chip 10 by known methods including solder, thermocompression bonding and reaction gold-aluminum bonding. Solderless bonds are preferred in hermetic packaging to prevent the introduction of debris into the package 26 and to avoid inadvertent spread of the solder to other areas of the chip.
It is accordingly, an object of the present invention to provide a novel method of covering a cellular semiconductor chip with a lid having electrode contacts on a lid lower surface in which the lid-to-chip alignment tolerances are not dictated by the alignment of the lid carried gate contacts with the gate electrode.
It is a further object of the prevent invention to provide a novel method of packaging a cellular semiconductor chip in which the package has lid-carried contacts for the chip electrodes and in which interdigitated gate runners are used to reduce effective series resistance in the chip gate electrode even though the lid-to-chip alignment tolerances exceed the width of the gate runners.
It is yet a further object to the present invention to provide a novel semiconductor chip in which plural interdigitated gate runners are applied to the chip in the same process step as the source electrode for the chip and in which each gate runner has a widened area for bonding to a lid-carried foil contact.
These and many other objects and advantages will be readily apparent to one skilled in the art to which the invention pertains from a perusal of the claims, the amended drawings and the following detailed description of preferred embodiments.